Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die

ABSTRACT

A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of the earlierU.S. Patent Application to Gordon Grivna, entitled “Semiconductor Deviceand Method of Forming Backside Openings for an Ultra-thin SemiconductorDie,” application Ser. No. 16/035,838, filed Jul. 16, 2018, now pending;which application is a division of the U.S. Patent Application to GordonGrivna, entitled “Semiconductor Device and Method of Forming BacksideOpenings for an Ultra-thin Semiconductor Die,” application Ser. No.15/452,888, filed Mar. 8, 2017, now U.S. Pat. No. 10,074,611, issuedSep. 11, 2018, the disclosures of each of which are hereby incorporatedentirely herein by reference.

TECHNICAL FIELD

The present disclosure relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of formingbackside openings for an ultra-thin semiconductor die.

BACKGROUND

A semiconductor wafer or substrate can be made with a variety of basesubstrate materials, such as silicon (Si), germanium, aluminumphosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride(GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indiumphosphide, silicon carbide (SiC), or other bulk material for structuralsupport. A plurality of semiconductor die is formed on the waferseparated by a non-active, inter-die substrate area or saw street. Thesaw street provides cutting areas to singulate the semiconductor waferinto individual semiconductor die.

In a vertical semiconductor device, the primary current path is verticalfrom the top surface of the die to a back surface of the die. Thevertical resistance, e.g., drain-source resistance (RDSON) of a verticaltransistor, decreases with the thickness of the semiconductor die. Tominimize vertical resistance, the semiconductor die should be as thin aspossible while still maintaining structural integrity. An opening can beformed in the back surface to reduce thickness of the semiconductor dieand vertical resistance. A thick metal layer, such as 25 micrometers(μm) copper, is formed across the back surface and into the opening forstructural support and electrical interconnect. Unfortunately, cuttingthrough the thick metal layer within the saw street to separate thesemiconductor die can be difficult and impose premature wear andexcessive cutting debris on the saw blade.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1a-1b illustrate a semiconductor substrate with a plurality ofsemiconductor die separated by a saw street;

FIGS. 2a-2l illustrate a process of forming a backside opening to enablelift-off of a backside metal;

FIG. 3 illustrates the semiconductor die of FIGS. 2a-2l postsingulation;

FIGS. 4a-4n illustrate a process of forming honeycomb pattern of basesubstrate material for support of ultra-thin semiconductor die; and

FIG. 5 illustrates the semiconductor die of FIGS. 4a-4n postsingulation.

DETAILED DESCRIPTION OF THE DRAWINGS

The following describes one or more embodiments with reference to thefigures, in which like numerals represent the same or similar elements.While the figures are described in terms of the best mode for achievingcertain objectives, the description is intended to cover alternatives,modifications, and equivalents as may be included within the spirit andscope of the disclosure. The term “semiconductor die” as used hereinrefers to both the singular and plural form of the words, andaccordingly, can refer to both a single semiconductor device andmultiple semiconductor devices.

FIG. 1a shows a semiconductor wafer or substrate 100 with a basesubstrate material 102, such as Si, germanium, aluminum phosphide,aluminum arsenide, GaAs, GaN, AlGaN/GaN, indium phosphide, SiC, or otherbulk material for structural support. Semiconductor substrate 100 has awidth or diameter of 100-450 millimeters (mm) and thickness of about700-800 micrometers (μm). A plurality of semiconductor die 104 is formedon substrate 100 separated by a non-active, inter-die substrate area orsaw street 106. Saw street 106 provides cutting areas to singulatesemiconductor substrate 100 into individual semiconductor die 104.

FIG. 1b shows a cross-sectional view of a portion of semiconductorsubstrate 100. Each semiconductor die 104 includes a back surface 108and active surface or region 110 containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and electrically interconnectedaccording to the electrical design and function of the die. For example,the circuit may include one or more transistors, diodes, and othercircuit elements formed within active surface or region 110 to implementanalog circuits or digital circuits. In one embodiment, semiconductordie 104 implements a diode, transistor, or other discrete semiconductordevice. In a vertical transistor, the gate region and source region aretypically accessible on active surface 110, and the drain region of thevertical transistor is back surface 108. Semiconductor die 104 may alsocontain a digital signal processor (DSP), microcontroller, ASIC,standard logic, amplifiers, clock management, memory, interface circuit,optoelectronics, and other signal processing circuits. Semiconductor die104 may also contain integrated passive devices (IPDs), such asinductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer 112 is formed over active surface 110using PVD, CVD, electrolytic plating, electroless plating process, orother suitable metal deposition process. Conductive layer 112 includesone or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni),gold (Au), silver (Ag), titanium (Ti), titanium tungsten (TiW), TiNiCu,TiNiAg, or other suitable electrically conductive material. Conductivelayer 112 operates as contact pads electrically connected to thecircuits, e.g., gate region and source region of the verticaltransistor, on active surface 110.

FIGS. 2a-2l show a process of forming a backside opening to achieve anultra-thin semiconductor die and enable lift-off of a backside metalwithout singulation through the backside metal. In FIG. 2a ,semiconductor substrate 100 is positioned with active surface 110oriented toward carrier or backgrinding tape 120. In FIG. 2b , aninterior region of back surface 108 a of semiconductor substrate 100 isthinned with grinding wheel 122, leaving a thick support ring 124 arounda perimeter of the semiconductor substrate. FIG. 2c illustrates backsurface 108 b, after thinning, of semiconductor substrate 100 withoptional support ring 124 for structural support. In one embodiment,semiconductor wafer 100 has a thickness of 90-150 μm between activesurface 110 and back surface 108 b.

In FIG. 2d , photoresist layer 126 is formed over back surface 108 b ofsemiconductor substrate 100. Photoresist layer 126 is patterned withopenings 128 over back surface 108 b. There is one opening 128 alignedwith each semiconductor die 104.

In FIG. 2e , a plurality of openings 130 is formed partially into backsurface 108 b but not completely through base substrate material 102through openings 128 by isotropic etching, non-isotropic etching, orlaser direct ablation (LDA). Photoresist layer 126 covers any laser markarea of semiconductor substrate 100 to avoid forming opening 130 withinthe laser mark area.

FIG. 2f shows a cross-sectional view, taken along line 2 f-2 f of FIG.2e , of a portion of semiconductor substrate 100 with support ring 124and openings 130 partially through base substrate material 102. Inparticular, each opening 130 is formed over one semiconductor die 104,i.e., the boundaries of the opening align with the boundaries of thesemiconductor die. In one embodiment, openings 130 have a width of 2000μm and depth of 65-75 μm. The isotropic etch leaves pillars 132 of basesubstrate material 102 between openings 130 in an area defining sawstreets 106. In one embodiment, pillars 132 have a width of 20 μm. Aportion of photoresist layer 126 remains over pillars 132. Surface 136defines the bottom of opening 130 and the new back surface ofsemiconductor die 104.

In FIG. 2g , an electrically conductive layer 134 is formed over thepedestal defined by photoresist layer 126 on pillars 132 and intoopenings 130 over surface 136 using evaporation, sputtering, PVD, CVD,or other suitable metal deposition process. Conductive layer 134includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, TiNiCu,or other suitable electrically conductive material. In one embodiment,conductive layer 134 has a thickness of 20-50 μm or more to providesupport for the ultra-thin semiconductor die 104. In particular,conductive layer portion 134 a is formed over the pedestal defined byphotoresist layer 126 on pillars 132, and conductive layer portion 134 bis formed into openings 130 over surface 136. Photoresist layer 126 onpillars 132 of base substrate material 102 elevates and separatesconductive layer portion 134 a with respect to conductive layer portion134 b in openings 130.

In FIG. 2h , conductive layer portion 134 a is removed or lifted-off bydissolving photoresist layer 126 using a solvent spray or bath withultrasonic action. The solvent does not remove conductive layer portion134 b, which remains over surface 136 of semiconductor die 104.Alternatively, the lift-off of conductive layer portion 134 a can bedone with a hard-mask for wet etched openings 130. A portion of pillars132 of base substrate material 102 may remain between semiconductor die104 after lift-off of conductive layer portion 134 a. The surface levelof conductive layer 134 a may be less than or greater than the surfacelevel of pillars 132. The lift-off of conductive layer portion 134 aeliminates the singulation issues of the saw blade cutting through thickmetal, as described in the background.

In FIG. 2i , an edge pattern 138 is an opening formed in photoresistlayer 126 around a perimeter of semiconductor substrate 100. A thickermetal is more difficult to lift-off. Edge pattern opening 138 provides abreak to assist with lift-off of thicker conductive layer 134 a forsemiconductor die 104 having side surfaces proximate to the perimeter ofsemiconductor substrate 100. The continuous break of conductive layer134 a extends around the perimeter of semiconductor substrate 100 bynature of edge pattern opening 138.

In FIG. 2j , semiconductor substrate 100 with backgrinding tape 120 isinverted with back surface 136 and conductive layer portion 134 boriented toward carrier 140. Semiconductor substrate 100 is mounted tocarrier 140 and backgrinding tape 120 is removed. Optional support ring124 can provide additional support of the thinned semiconductorsubstrate 100 during wafer handling.

In FIG. 2k , semiconductor substrate 100 is again inverted with activesurface 110 and conductive layer 112 oriented toward dicing tape 144.Semiconductor substrate 100 is mounted to dicing tape 144.

In FIG. 2 l, semiconductor substrate 100 is singulated through sawstreet 106 and pillars 132 by plasma etching. Plasma etching hasadvantages of forming precision side surfaces along saw streets 106,while retaining the structure and integrity of the base substratematerial. Alternatively, semiconductor substrate 100 is singulatedthrough saw street 106 and pillars 132 using a saw blade or lasercutting tool 146 into individual semiconductor die 104. The singulationoccurs without cutting through a thick conductive layer. Support ring124 is also removed during singulation. Support ring 124 could have beenremoved in FIG. 2 h.

FIG. 3 shows ultra-thin semiconductor die 104 post singulation. In oneembodiment, semiconductor die 104 has a thickness of 50 μm, i.e., 25 μmfor base substrate material 102 and conductive layer 112, and 25 μm forconductive layer 134 b. In some embodiments toward the edge of the die104, conductive layer 134 may decrease in thickness and substrate 110may increase in thickness. Conductive layer 112 provides electricalconnection for the source region and gate region of the verticaltransistor. Conductive layer 134 b is formed within openings 130, whileconductive layer 134 a is formed over photoresist layer 126 on pillars132. Photoresist layer 126 is removed to lift-off conductive layerportion 134 a. Conductive layer 134 b remains on back surface 136 ofsemiconductor die 104 after the lift-off to provide electricalconnection for the drain region of the vertical transistor. The lift-offof conductive layer 134 a allows semiconductor substrate 100 to besingulated through saw street 106 and pillars 132, without the need tocut through a thick metal layer.

FIGS. 4a-4n show a process of forming a plurality of backside openingsfor an ultra-thin semiconductor die. Continuing from FIG. 2c , aphotoresist layer 150 is formed over back surface 108 b of semiconductorsubstrate 100, as shown in FIG. 4a . Photoresist layer 150 is patternedwith offset hexagon-shaped openings 152 over back surface 108 b, oralternate opening shapes such as circles, rectangles, lines, orcombinations of each. There are many openings 152 for each semiconductordie.

In FIG. 4b , a plurality of hexagon-shaped openings 160 is formedpartially into back surface 108 b but not completely through basesubstrate material 102 through openings 152 by isotropic etching ornon-isotropic etching that is independent of substrate 100 crystalorientation. The hexagon-shaped openings 160 are arranged in an offsetpattern of multiple rows formed partially into base substrate material102 within the boundaries of one semiconductor die 104. In oneembodiment, openings 160 each have a width of 200 μm or less and depthof 65-75 μm for a 2 mm by 2 mm semiconductor die 104. Photoresist layer150 covers any laser mark area of semiconductor substrate 100 to avoidforming opening 160 within the laser mark area.

FIG. 4c shows a cross-sectional view, taken along line 4 c-4 c of FIG.4b , of a portion of semiconductor substrate 100 with support ring 124and openings 160 disposed on carrier or backgrinding tape 162. Supportring 124 can be formed separately or simultaneously as pillars 164 byusing photoresist layer 150. A portion of photoresist layer 150 remainsover base substrate material 102 between openings 152 to form openings160. Photoresist layer 150 between openings 152 leaves base substratematerial 102 between each opening 160, i.e., under photoresist layer 150between adjacent openings 152. Base substrate material 102 has ahoneycomb pattern 164 around the offset pattern of openings 160 overback surface 108 b of semiconductor die 104, see FIG. 4d . The thicknessof honeycomb pattern 164 of base substrate material 102 over backsurface 108 b of semiconductor die 104 is the thickness of semiconductorsubstrate 100, i.e., 90-150 μm, for structural support of semiconductordie 104. Openings 160 make up the vast majority of the area ofsemiconductor die 104 ultra-thin for low on-resistance. In other words,the thickness of semiconductor die 104 between active surface 110 andthe bottom of each opening 160 is about 20-50 μm. The large number ofopenings 160 across a surface area of semiconductor die 104 allows themajority of drain current to flow through the ultra-thin base substratematerial 102 to achieve the low on-resistance. The honeycomb pattern 164of base substrate material 102 over back surface 108 b of semiconductordie 104 take little area but provides support for the remainingultra-thin regions of semiconductor die 104.

FIG. 4e shows another embodiment with region 166 of photoresist layer150 between rows of honeycomb pattern 164. Region 166 of photoresistlayer 150 leaves base substrate material 102 between the rows ofhoneycomb pattern 164 for additional support. Other patterns of openings160 can be formed in base substrate material 102. For example, there canbe base substrate material 102 between columns of honeycomb pattern 164for additional support. FIG. 4f shows regions 168 of photoresist layer150 disposed interstitially within honeycomb pattern 164. Regions 168 ofphotoresist layer 150 leave larger regions of base substrate material102 disposed interstitially within honeycomb pattern 164 for additionalsupport. Openings 160 in honeycomb pattern 164 still occupy the majorityof the area of semiconductor die 104 ultra-thin for low on-resistance.The large number of openings 160 across a surface area of semiconductordie 104 allows the majority of drain current to flow through theultra-thin base substrate material 102 to achieve the low on-resistance.The honeycomb pattern 164 of base substrate material 102 over backsurface 108 b of semiconductor die 104 take a small portion of the areabut provides support for the remaining ultra-thin regions ofsemiconductor die 104.

FIG. 4g shows another embodiment with a high aspect ratio semiconductordie 104 offset on semiconductor substrate 100. In this case, the lengthof semiconductor die 104 is greater than its width. The boundaries ofthe offset pattern of hexagon-shaped openings 160 align with theboundaries of semiconductor die 104. The offset pattern of openings 160leaves base substrate material 102 between each opening 160, i.e., underphotoresist layer 150 between adjacent openings 152. Base substratematerial 102 has a honeycomb pattern 170 around the offset pattern ofopenings 160 over back surface 108 b of semiconductor die 104. Openings160 make the vast majority of the area of semiconductor die 104ultra-thin for low on-resistance. Honeycomb pattern 170 of basesubstrate material 102 over back surface 108 b of semiconductor die 104take little area but provides support for remaining ultra-thin regionsof semiconductor die 104. The remaining photoresist layer 150 betweensemiconductor die 104 leaves additional base substrate material 102 toprovide additional support.

FIG. 4h shows yet another embodiment with a high aspect ratiosemiconductor die 104 offset on semiconductor substrate 100. Theboundaries of the offset pattern of hexagon-shaped openings 160 alignwith the boundaries of semiconductor die 104. The offset pattern ofopenings 160 leaves base substrate material 102 between each opening160, i.e., under photoresist layer 150 between adjacent openings 152.Base substrate material 102 has a honeycomb pattern 176 around theoffset pattern of openings 160 over back surface 108 b of semiconductordie 104. Openings 160 make the vast majority of the area ofsemiconductor die 104 ultra-thin for low on-resistance. Honeycombpattern 176 of base substrate material 102 over back surface 108 b ofsemiconductor die 104 take little area but provides support forremaining ultra-thin regions of semiconductor die 104. The remainingphotoresist layer 150 between semiconductor die 104 leaves additionalbase substrate material 102 to provide additional support and can act asa solder dam to control solder movement. Additional base substratematerial separate from the honeycomb structures, can be retainedinterior to the die for additional structural support.

Returning to FIG. 4d , photoresist layer 150 is removed and anelectrically conductive layer 180 is formed over honeycomb pattern 164of base substrate material 102 and into openings 160 using evaporation,sputtering, PVD, CVD, or other suitable metal deposition process, asshown in FIG. 4i . FIG. 4j shows a plan view of conductive layer 180formed over honeycomb pattern 164 of base substrate material 102 andinto openings 160. FIG. 4k shows adjacent openings 160 in honeycombpattern 164 of base substrate material 102 covered by conductive layer180, including the top surface, side surfaces, and bottom surface of thestructure. Conductive layer 180 includes one or more layers of Al, Cu,Sn, Ni, Au, Ag, Ti, TiW, TiNiCu, TiNiAg, or other suitable electricallyconductive material. Conductive layer 180 provides electrical connectionfor the drain region of the vertical transistor. Conductive layer 180 ismade relatively thin, e.g., 0.5-1.5 μm or less, because the primarysupport for the ultra-thin semiconductor die 104 is realized withhoneycomb pattern 164 of base substrate material 102.

In FIG. 4 l, support ring 124 may be removed by a saw blade or lasercutting tool 184.

In FIG. 4m , semiconductor substrate 100 with backgrinding tape 120 isinverted with back surface 108 b and conductive layer 180 orientedtoward dicing tape 186. Semiconductor substrate 100 is mounted to dicingtape 186. Backgrinding tape 162 is removed.

In FIG. 4n , semiconductor substrate 100 is singulated through sawstreet 106 by plasma etching. Plasma etching has advantages of formingprecision side surfaces along saw streets 106, while retaining thestructure and integrity of the base substrate material. Alternatively,semiconductor substrate 100 is singulated through saw street 106 using asaw blade or laser cutting tool 188 into individual semiconductor die104. Plasma etch or saw blade 188 easily cuts or breaks through therelatively thin conductive layer 180. Honeycomb patterns 170 and 176 ofbase substrate material 102 for offset semiconductor die 104 in FIGS.4g-4h would follow the same process of FIGS. 4i -4 n.

FIG. 5 shows semiconductor die 104 post singulation. Conductive layer112 provides electrical connection for the source region and gate regionof the vertical transistor. Honeycomb pattern 164 of base substratematerial 102 provides structural support for semiconductor die 104.Conductive layer 180 provides electrical connection for the drain regionof the vertical transistor. Semiconductor die 104 with honeycomb pattern164 is robust during die handling, while retaining a low on-resistancethrough the ultra-thin portions of the die. The relatively thinconductive layer 180 can be easily cut or broken by plasma etch or sawblade without the singulation issues encountered by the thick metallayer.

While one or more embodiments have been illustrated and described indetail, the skilled artisan will appreciate that modifications andadaptations to those embodiments may be made without departing from thescope of the present disclosure.

What is claimed is:
 1. A method of making a semiconductor device, themethod comprising: providing a semiconductor substrate including aplurality of semiconductor die; forming a plurality of openings over theplurality of semiconductor die, the plurality of openings extendingpartially into a surface of the semiconductor substrate; and afterforming the plurality of openings, forming a conductive layer on thesurface of the semiconductor substrate and into the plurality ofopenings.
 2. The method of claim 1, wherein the plurality of openingsare arranged in multiple offset rows.
 3. The method of claim 2, whereina boundary of the multiple offset rows corresponds with a boundary of arespective semiconductor die of the plurality of semiconductor die. 4.The method of claim 1, wherein the plurality of openings comprise one ofa hexagonal shape, a circular shape, a rectangular shape, a linearshape, or any combination thereof.
 5. The method of claim 1, wherein theplurality of openings is one of a polygonal shape or an ellipticalshape.
 6. The method of claim 1, further comprising forming a supportring simultaneously with the plurality of openings.
 7. The method ofclaim 1, further comprising forming a support ring separately fromforming the plurality of openings.
 8. A method of making a semiconductordevice, the method comprising: providing a semiconductor substrateincluding a plurality of semiconductor die; forming a plurality ofopenings each comprising a closed shape over the plurality ofsemiconductor die, the plurality of openings extending into a surface ofthe semiconductor substrate; and after forming the plurality ofopenings, forming a conductive layer on the surface of the semiconductorsubstrate and into the plurality of openings.
 9. The method of claim 8,wherein the plurality of openings are arranged in multiple offset rows.10. The method of claim 9, wherein a boundary of the multiple offsetrows corresponds with a boundary of a respective semiconductor die ofthe plurality of semiconductor die.
 11. The method of claim 8, whereinthe closed shape comprises one of a hexagonal shape, a circular shape, arectangular shape, a linear shape, or any combination thereof.
 12. Themethod of claim 8, wherein the closed shape comprises a polygonal shapeor an elliptical shape.
 13. The method of claim 8, further comprisingforming a support ring simultaneously with the plurality of openings.14. The method of claim 8, further comprising forming a support ringseparately from forming the plurality of openings.
 15. A method ofmaking a semiconductor device, the method comprising: providing asemiconductor substrate including a plurality of semiconductor die;forming a pattern of a plurality of openings each comprising a closedshape over the plurality of semiconductor die, the plurality of openingsformed in a surface of the semiconductor substrate; and after formingthe pattern, forming a conductive layer on the pattern.
 16. The methodof claim 15, wherein the closed shape comprises one of a hexagonalshape, a circular shape, a rectangular shape, a linear shape, or anycombination thereof.
 17. The method of claim 15, wherein the closedshape comprises a polygonal shape or an elliptical shape.
 18. The methodof claim 15, further comprising forming a support ring simultaneouslywith the plurality of openings.
 19. The method of claim 15, furthercomprising forming a support ring separately from forming the pluralityof openings.
 20. The method of claim 15, wherein forming the patternfurther comprises: forming the pattern on the semiconductor substrateusing a photoresist; etching the plurality of openings into thesemiconductor substrate; and removing the photoresist.